EC4870 VLSI Systems Design

Introduction to the design and implementation of Complementary Metal Oxide Semiconductor (CMOS) and Bipolar CMOS (BiCMOS) Very Large Scale Integration (VLSI) digital Integrated Circuits (ICs). Topics covered include the specification of the high-level functional design, the design, implementation, and simulation of low-level cells, floor planning and the assembly of low-level cells into the high-level design using hierarchical place-and-route techniques, circuit extraction and simulation for functional verification, timing analysis, and power estimation, and the principles of bulk CMOS, BiCMOS, and SOS/SOI IC fabrication. Applications of VLSI ICs in military systems are also covered. The course is centered around laboratory projects where student groups design, implement, simulate, and submit for fabrication, a full-custom CMOS or BiCMOS, VLSI IC. IC functionality is selected by each student group. A field trip to a commercial foundry and clean room tour is also included.

Prerequisite

EC2200 and either EC3800 or EC3830 or EC3840

Lecture Hours

3

Lab Hours

2

Course Learning Outcomes

·       Given a systems problem in the field of Electrical and Computer Engineering that is solvable with a VLSI digital or mixed-signal IC, the student will be able to specify the hierarchical design of a CMOS or BiCMOS IC capable of solving the problem, including the specifications for all cells at all levels of the design hierarchy.

·       Given the specification for either a combinatorial or sequential digital logic circuit, the student will be able to design a CMOS or BiCMOS circuit that implements the specification, including full characterization of the circuit with respect to noise margins, speed, and power consumption.

·       Given the design of a CMOS or BiCMOS digital, analog, or mixed-signal circuit and a set of suitable IC mask design rules, the student will be able to design and lay out the mask for the circuit.

·       Given the mask design of a CMOS or BiCMOS circuit and appropriate process parameters, the student will be able to estimate the parasitic resistance and capacitance in the layout and estimate RC delays, circuit speed, and power consumption.

·       Given a specification for a CMOS or BiCMOS VLSI digital or mixed-signal IC and a library of low-level cells, the student will be able to implement the specification using a well-structured, hierarchical design, including estimating speed and power consumption.